Exciting engineering opportunity in research and development as a key member of a very early stage technology start up company based in San Diego near the UC San Diego campus.
Candidate will work with advanced SOI technology to create wide-band front-end modules and components in a dynamic team.
MS/PhD degree with hands-on experience in RFIC/MMIC circuit design using bulk/SOI CMOS technologies. Solid knowledge of RFIC/MMIC design and device physics, experience with RF and analog layout. Strong understanding of wideband Tx/Rx chain tradeoffs in relation to output power, gain, crosstalk, linearity and bandwidth. Experience in component design, modelling and simulation using EMX and HFSS. Able to develop test and characterization plans for designed blocks. Strong problem-solving skills. Must be a self-starter with excellent communication skills who is willing to share and help in a team environment.
RFIC Layout Engineers
Job descriptionLayout mask design for wideband transceiver IC, including: Floor planning, pad frame design, tape-out.
- Layout of analog, RF, and blocks using Cadence PVS
- DRC, LVS, and parasitic extraction
- LVS/DRC rule file creating, editing
- Scripting/coding using SKILL
- Collaboration with circuit designers on iterative, performance-driven layout changes
- At least 5 years of experience in high frequency RF/analog IC layout in a product development environment
- Experience with layout in SOI technology and latest Cadence tool.
- Profficient with Cadence tools for layout, verification, and parasitic extraction
- Understand layout techniques for improving matching, reliability, and manufacturability, reducing performance degradation by parasitics, and mitigating ESD
- Ability to take full advantage of productivity-enhancing features of layout tools and to use scripts to further increase productivity
- Self-motivated and proactive in identifying and solving problems
- Ability to work well and communicate effectively with other team members and management